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publication number S71WS-J_04 revision a amendment 2 issue date august 19, 2005 S71WS-J based mcps stacked multi-chip product (mcp) 128/64 megabit (8m/4m x 16 -bit) cmos 1.8 volt-only, simultaneous read/write, burst mode flash memory with cosmoram data sheet preliminary

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( S71WS-J based mcps stacked multi-chip product (mcp) 128/64 megabit (8m/4m x 16-bit) cmos 1.8 volt-only, simultaneous read/write, burst mode flash memory with cosmoram data sheet preliminary flash memory density 256mb 128mb 64mb ") 9:4 =8.ab9f!? =8.8a7f!? ga4 =8.8a7f;? =8.?9:f;? 894 =8.8a7f#? =8.?9:f#?
2 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary product selector guide device-model# flash density psram density flash speed (mhz) psram speed (mhz/ns) supplier package availability status =8.?9:f#?%ah 9:4 894 99 99i=? !e#4 =+>+8a 7?% =8.?9:f;?%ah ga4 !e#4 =8.8a7f#?%#h 8a74 !e#4 7+889+8a 7:% =8.8a7f;?%#h !e#4 =8.8a7f!?%#h 9:4 !e#4 =8.ab9f!?%h ab94 !e#4 7+889+8: 7:%
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 3 preliminary S71WS-J based mcps notice on data sheet designations . . . . . . . . . . . ii advance information .......................................................................................ii preliminary ..........................................................................................................ii combination .......................................................................................................ii full production (no designation on document) ...................................ii mcp features ........................................................................................................ 1 product selector guide . . . . . . . . . . . . . . . . . . . . . 2 mcp block diagram .............................................................................................6 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 7 lookahead connection diagram . . . . . . . . . . . . 10 input/output descriptions . . . . . . . . . . . . . . . . . . . 11 ordering information . . . . . . . . . . . . . . . . . . . . . . 12 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . 14 tla08484-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package ........................................................................................... 14 fta08484-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package ............................................................................15 tlc08080-ball fine-pitch ball grid array (fbga) 7 x 9 mm package ............................................................................... 16 tsc080 - fine-pitch ball grid arra y (fbga) 7 x 9 mm package .........17 s29ws128/064j general description . . . . . . . . . . . . . . . . . . . . . . . .20 product selector guide . . . . . . . . . . . . . . . . . . . . . 22 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 block diagram of simultaneous operation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 23 input/output descriptions . . . . . . . . . . . . . . . . . . .24 device bus operations . . . . . . . . . . . . . . . . . . . . . . 25 8 ;
1 ab versatileio? (v io ) control .............................................................................25 requirements for asynchronous read operation (non-burst) ..........25 requirements for synchronous (burst) read operation ...................... 26 8-, 16-, and 32-word linear burst with wrap around ......................27 a;
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a= configuration register ......................................................................................27 handshaking ..........................................................................................................27 simultaneous read/write operations with zero latency ................... 28 writing commands/command sequences ................................................ 28 accelerated program operation ..... ............................................................. 28 autoselect mode ................................................................................................ 29 g#
!204 g? sector/sector block protection and unprotection ................................. 30 :a>.8a7i?9:fj4!; i ; '# ik g? ba>.?9:f; i ; '# ik ga sector protection ............................. ..............................................................34 persistent sector protection ...........................................................................34 persistent protection bit (ppb) ..................................................................35 persistent protection bit lock (ppb lock) .............................................35 dynamic protection bit (dyb) ...................................................................35 9 g9 persistent sector protection mode locking bit ........................................37 password protection mode .............................................................................37 password and password mode lockin g bit ................................................37 64-bit password ...................................................................................................38 persistent protection bit lock ..... .................................................................. 38 standby mode ...................................................................................................... 39 automatic sleep mode ..................................................................................... 39 reset#: hardware reset input ...... .......................................................... 39 output disable mode ...................................................................................40 ,
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# :a secured silicon sector protection bit ...................................................... 43 hardware data protection ............... .......................................................... 43 write protect (wp#) .......................................................................................44 low v cc write inhibit .................................................................................44 write pulse glitch protection . ..............................................................44 logical inhibit ...................................................................................................44 power-up write inhibit ...............................................................................44 common flash memory interface (cfi) . . . . . . . 45 7!,$3
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:= 8a.8a7f # :7 8g.?9:f # b9 command definitions . . . . . . . . . . . . . . . . . . . . . . 62 reading array data ........................................................................................... 62 set configuration register command sequence ..................................... 62 ,
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e 99 reset command .................................................................................................66 autoselect command sequence .......... .......................................................... 67 enter/exit secured silicon sector command sequence ......................... 67 program command sequence ........................................................................68 unlock bypass command sequence .. ......................................................68 ,
:1 9> chip erase command sequence ...................................................................69 sector erase command sequence ................................................................70 erase suspend/erase resume command s ................................................... 71 ,
b-1 =a password program command ............. .......................................................... 72 password verify command ............................................................................. 73 password protection mode lockin g bit program command .............. 73 persistent sector protection mode locking bit program command ........................................................................................... 73 secured silicon sector protection bit program command .................. 73 ppb lock bit set command ............................................................................ 74 dpb write/erase/status command ... .......................................................... 74 password unlock command .......................................................................... 74 ppb program command .................................................................................. 75 all ppb erase command .................................................................................. 75 ppb status command ....................................................................................... 75 ppb lock bit status command ...................................................................... 75 command definitions ....................................................................................... 76 87! =9
4 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary write operation status . . . . . . . . . . . . . . . . . . . . .79 dq7: data# polling ............................................................................................79 ,
9l #7? dq6: toggle bit i ................................................................................................ 81 ,
=;#7a dq2: toggle bit ii .............................................................................................. 82 8>39 3a$ 7g reading toggle bits dq6/dq2 ......................................................................83 dq5: exceeded timing limits ....................................................................... 84 dq3: sector erase timer ................................................................................ 84 a?.1
7b absolute maximum ratings . . . . . . . . . . . . . . . . . 85 ,
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8g! m! & >? ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 91 synchronous/burst read @ v io = 1.8 v ...................................................... 91 ,
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g=; '%%; 'ei.! 88a cosmoram features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 pin description (32m) . . . . . . . . . . . . . . . . . . . . . . 114 functional description . . . . . . . . . . . . . . . . . . . . . 115 asynchronous operation (page mode) .......................................................115 functional description . . . . . . . . . . . . . . . . . . . . . 116 synchronous operation (burst mode ) ........................................................116 state diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 initial/standby state ............................................................................................117 ,
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1 887 functional description . . . . . . . . . . . . . . . . . . . . . 118 power-up ...............................................................................................................118 configuration register ......................................................................................118 cr set sequence ................................................................................................118 power down ........................................................................................................121 burst read/write operation ................ ..........................................................121 ,
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:ge 8a: address latch by adv# .................................................................................125 burst length ........................................................................................................125 single write .........................................................................................................125 write control ....................................................................................................126 ,
::.! 8a9 burst read suspend ..........................................................................................126 ,
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. 8a7 absolute maximum ratings . . . . . . . . . . . . . . . . 129 recommended operating conditions (see warning below) . . . . . . . . . . . . . . . . . . . . . . . . . . 129 package pin capacitance . . . . . . . . . . . . . . . . . . . 129 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 130 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 131 read operation ..................................................................................................131 write operation ............................................................................................... 133 synchronous operation - clock input (burst mode) ............................134 synchronous operation - address latc h (burst mode) .......................134 synchronous read operation (burst mode) ............................................ 135 synchronous write operation (burst mode) ..........................................136 power down parameters ............................................................................... 137 other timing parameters ............................................................................... 137 ac test conditions ......................................................................................... 137 ac measurement output load circuit .....................................................138 ,
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 5 preliminary timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139 ,
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1 897 cosmoram type 1 C 1.8 v, 16 mb features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 general description . . . . . . . . . . . . . . . . . . . . . . . 169 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 function truth table . . . . . . . . . . . . . . . . . . . . . . 171 absolute maximum ratings . . . . . . . . . . . . . . . . 171 recommended operating conditions . . . . . . . . 171 package pin capacitance . . . . . . . . . . . . . . . . . . . 172 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 172 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 172 read operation .................................................................................................172 write operation .............................................................................................. 173 power down parameters ...............................................................................174 other timing parameters ...............................................................................174 ac test conditions .........................................................................................174 ac measurement output load circuit .....................................................174 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 175 ,
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8?= - e. 87a revision summary . . . . . . . . . . . . . . . . . . . . . . . . 183 revision summary
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 7 preliminary connection diagrams (cosmoram type-based) 123

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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 13 preliminary s71ws064jb0 valid combinations (ws064j flash + 32mb psram) material set supplier base ordering part number package marking temperature range burst speed =8.?9:f;?;#.ah =8.?9:f;?;#.ah %abc!d7bc! 9942& % !e#4 =8.?9:f;?;,.ah =8.?9:f;?; ,.ah %abc!d7bc! % s71ws128ja0 valid combinations (ws128j flash + 16mb psram) material set supplier base ordering part number package marking temperature range burst speed =8.8a7f#?;#.#h =8.8a7f#?;#.#h %abc!d7bc! 9942& % !e#4 =8.8a7f#?;,.#h =8.8a7f#?;,.#h %abc!d7bc! % s71ws128jb0 valid combinations (ws128j flash + 32mb psram) material set supplier base ordering part number package marking temperature range burst speed =8.8a7f;?;#.#h =8.8a7f;?;#.#h %abc!d7bc! 9942& % !e#4 =8.8a7f;?;,.#h =8.8a7f;?;,.#h %abc!d7bc! % s71ws128jc0 valid combinations (ws128j flash + 64mb psram) material set supplier base ordering part number package marking temperature range burst speed =8.8a7f!?;#.#h =8.8a7f!?;#.#h %abc!d7bc! 9942& % !e#4 =8.8a7f!?;,.#h =8.8a7f!?; ,.#h %abc!d7bc! % s71ws256jc0 valid combinations (2 x ws128j flash + 64mb psram) material set supplier base ordering part number package marking temperature range burst speed =8.ab9f!?;#.h =8.ab9f!?;#.h %abc!d7bc! 9942& % !e#4 =8.ab9f!?;,.h =8.ab9f!?;, .h %abc!d7bc! % <,

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14 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary physical dimensions tla08484-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package 3372-2 \ 16-038.22a package tla 084 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10, e1,e10,f1,f10,g1,g10, h1,h10,j1,j10,k1,k10,l1,l10, m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a 0.15 c a b m c m 0.08 pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 15 preliminary fta08484-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package 3388 \ 16-038.21a package fta 084 jedec n/a d x e 11.60 mm x 8.00 mm note package symbol min nom max a --- --- 1.40 profile a1 0.17 --- --- ball height a2 1.02 --- 1.17 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10,e1,e10 f1,f10,g1,g10,h1,h10 j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. (2x) c 0.08 0.20 c c 6 b side view 84x a1 a2 a 0.15 m c mc ab 0.08 bottom view ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd a e b c 0.15 d c 0.15 (2x) index mark 10 top view corner pin a1
16 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary tlc08080-ball fine-pitch ball grid array (fbga) 7 x 9 mm package 3430 \ 16-038.22 \ 10.15.04 package tlc 080 jedec n/a d x e 9.00 mm x 7.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 9.00 bsc. body size e 7.00 bsc. body size d1 7.20 bsc. matrix footprint e1 5.60 bsc. matrix footprint md 10 matrix size d direction me 8 matrix size e direction n 80 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 6 b top view side view corner 80x a1 a2 a 0.15 m c mc ab 0.08 pin a1 j k e1 7 se a d1 ed dc e f g h 8 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view 10
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 17 preliminary tsc080 - fine-pitch ball grid array (fbga) 7 x 9 mm package 3496 \ 16-038.22 \ 5.20.05 package tsc 080 jedec n/a d x e 9.00 mm x 7.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 9.00 bsc. body size e 7.00 bsc. body size d1 7.20 bsc. matrix footprint e1 5.60 bsc. matrix footprint md 10 matrix size d direction me 8 matrix size e direction n 80 ball count ?b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 6 b side view 80x 0.15 m c 0.08 m c ab c c a d e index mark c 0.15 (2x) c 0.15 b (2x) c 9 top view corner a1 a a2 pin a1 0.20 0.08 e1 7 se a d1 ed b c d e f g h j 7 8 6 5 3 2 k 1 ee 4 corner pin a1 7 sd bottom view
publication number S71WS-J_04 revision a amendment 2 issue date august 19, 2005 preliminary s29ws128/064j flash family for mult i-chip products (mcp) 128/64 megabit (8/4 m x 16-bit) cmos 1.8 volt-only simultaneous read/write, burst mode flash memory distinctive characteristics 3

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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 31 preliminary #9 ????????88? :m" #= ????????888 :m" #7 ???????8rrr gam" #> ??????8?rrr gam" #8? ??????88rrr gam" #88@#8: ?????8rrrrr 8a7:+gam" #8b@#87 ????8?rrrrr 8a7:+gam" #8>@#aa ????88rrrrr 8a7:+gam" #ag%#a9 ???8??rrrrr 8a7:+gam" #a=%#g? ???8?8rrrrr 8a7:+gam" #g8%#g: ???88?rrrrr 8a7:+gam" #gb%#g7 ???888rrrrr 8a7:+gam" #g>%#:a ??8???rrrrr 8a7:+gam" #:g%#:9 ??8??8rrrrr 8a7:+gam" #:=%#b? ??8?8?rrrrr 8a7:+gam" #b8@#b: ??8?88rrrrr 8a7:+gam" #bb@#b7 ??88??rrrrr 8a7:+gam" #b>@#9a ??88?8rrrrr 8a7:+gam" #9g@#99 ??888?rrrrr 8a7:+gam" #9=@#=? ??8888rrrrr 8a7:+gam" #=8@#=: ?8????rrrrr 8a7:+gam" #=b@#=7 ?8???8rrrrr 8a7:+gam" #=>@#7a ?8??8?rrrrr 8a7:+gam" #7g@#79 ?8??88rrrrr 8a7:+gam" #7=@#>? ?8?8??rrrrr 8a7:+gam" #>8@#>: ?8?8?8rrrrr 8a7:+gam" #>b@#>7 ?8?88?rrrrr 8a7:+gam" #>>@#8?a ?8?888rrrrr 8a7:+gam" #8?g@#8?9 ?88???rrrrr 8a7:+gam" #8?=@#88? ?88??8rrrrr 8a7:+gam" #888@#88: ?88?8?rrrrr 8a7:+gam" #88b@#887 ?88?88rrrrr 8a7:+gam" #88>@#8aa ?888??rrrrr 8a7:+gam" #8ag@#8a9 ?888?8rrrrr 8a7:+gam" #8a=@#8g? ?8888?rrrrr 8a7:+gam" #8g8%#8g: ?88888rrrrr 8a7:+gam" #8gb%#8g7 8?????rrrrr 8a7:+gam" #8g>%#8:a 8????8rrrrr 8a7:+gam" #8:g%#8:9 8???8?rrrrr 8a7:+gam" #8:=%#8b? 8???88rrrrr 8a7:+gam" #8b8@#8b: 8??8??rrrrr 8a7:+gam" #8bb@#8b7 8??8?8rrrrr 8a7:+gam" #8b>@#89a 8??88?rrrrr 8a7:+gam" #89g@#899 8??888rrrrr 8a7:+gam" #89=@#8=? 8?8???rrrrr 8a7:+gam" ) aaj#a )? )4-),
32 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ta b l e 5 . s29ws064j boot sector/sector block addresses for protection/unprotection #8=8@#8=: 8?8??8rrrrr 8a7:+gam" #8=b@#8=7 8?8?8?rrrrr 8a7:+gam" #8=>@#87a 8?8?88rrrrr 8a7:+gam" #87g@#879 8?88??rrrrr 8a7:+gam" #87=@#8>? 8?88?8rrrrr 8a7:+gam" #8>8@#8>: 8?888?rrrrr 8a7:+gam" #8>b@#8>7 8?8888rrrrr 8a7:+gam" #8>>@#a?a 88????rrrrr 8a7:+gam" #a?g@#a?9 88???8rrrrr 8a7:+gam" #a?=@#a8? 88??8?rrrrr 8a7:+gam" #a88@#a8: 88??88rrrrr 8a7:+gam" #a8b@#a87 88?8??rrrrr 8a7:+gam" #a8>@#aaa 88?8?8rrrrr 8a7:+gam" #aag@#aa9 88?88?rrrrr 8a7:+gam" #aa=@#ag? 88?888rrrrr 8a7:+gam" #ag8@#ag: 888???rrrrr 8a7:+gam" #agb@#ag7 888??8rrrrr 8a7:+gam" #ag>@#a:a 888?8?rrrrr 8a7:+gam" #a:g@#a:9 888?88rrrrr 8a7:+gam" #a:=@#ab? 8888??rrrrr 8a7:+gam" #ab8@#ab: 8888?8rrrrr 8a7:+gam" #abb@#ab7 88888?rrrrr 8a7:+gam" #ab> 888888??rrr gam" #a9? 888888?8rrr gam" #a98 8888888?rrr gam" #a9a 88888888??? :m" #a9g 88888888??8 :m" #a9: 88888888?8? :m" #a9b 88888888?88 :m" #a99 888888888?? :m" #a9= 888888888?8 :m" #a97 8888888888? :m" #a9> 88888888888 :m" ) a#j#a )? )4-), #? ?????????? :m" #8 ?????????8 :m" #a ????????8? :m" #g ????????88 :m" #: ???????8?? :m" #b ???????8?8 :m" #9 ???????88? :m" #= ???????888 :m" #7 ??????8rrr gam" ) aaj#a )? )4-),
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 33 preliminary #> ?????8?rrr gam" #8? ?????88rrr gam" #88@#8: ????8rrrrr 8a7:+gam" #8b@#87 ???8?rrrrr 8a7:+gam" #8>@#aa ???88rrrrr 8a7:+gam" #ag%#a9 ??8??rrrrr 8a7:+gam" #a=%#g? ??8?8rrrrr 8a7:+gam" #g8%#g: ??88?rrrrr 8a7:+gam" #gb%#g7 ??888rrrrr 8a7:+gam" #g>%#:a ?8???rrrrr 8a7:+gam" #:g%#:9 ?8??8rrrrr 8a7:+gam" #:=%#b? ?8?8?rrrrr 8a7:+gam" #b8@#b: ?8?88rrrrr 8a7:+gam" #bb@#b7 ?88??rrrrr 8a7:+gam" #b>@#9a ?88?8rrrrr 8a7:+gam" #9g@#99 ?888?rrrrr 8a7:+gam" #9=@#=? ?8888rrrrr 8a7:+gam" #=8@#=: 8????rrrrr 8a7:+gam" #=b@#=7 8???8rrrrr 8a7:+gam" #=>@#7a 8??8?rrrrr 8a7:+gam" #7g@#79 8??88rrrrr 8a7:+gam" #7=@#>? 8?8??rrrrr 8a7:+gam" #>8@#>: 8?8?8rrrrr 8a7:+gam" #>b@#>7 8?88?rrrrr 8a7:+gam" #>>@#8?a 8?888rrrrr 8a7:+gam" #8?g@#8?9 88???rrrrr 8a7:+gam" #8?=@#88? 88??8rrrrr 8a7:+gam" #888@#88: 88?8?rrrrr 8a7:+gam" #88b@#887 88?88rrrrr 8a7:+gam" #88>@#8aa 888??rrrrr 8a7:+gam" #8ag@#8a9 888?8rrrrr 8a7:+gam" #8a=@#8g? 8888?rrrrr 8a7:+gam" #8g8 88888??rrr gam" #8ga 88888?8rrr gam" #8gg 888888?rrr gam" #8g: 8888888??? :m" #8gb 8888888??8 :m" #8g9 8888888?8? :m" #8g= 8888888?88 :m" #8g7 88888888?? :m" #8g> 88888888?8 :m" #8:? 888888888? :m" #8:8 8888888888 :m" ) a#j#a )? )4-),
34 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary )
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40 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ."
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 41 preliminary figure 2. in-system sector protection/se ctor unprotection algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a7:a0 = 00000010 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a7:a0 = 01000010 set up first sector address wait 1.5 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
42 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary secured silicon sector flash memory region

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46 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary table 9. system interface string ta b l e 1 0 . device geometry definition

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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 47 preliminary table 11. primary vendor-specific extended query

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48 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary table 12. ws128j sector address table 4
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; ' #? :m" ??????%???,,, #8 :m" ??8???%??8,,, #a :m" ??a???%??a,,, #g :m" ??g???%??g,,, #: :m" ??:???%??:,,, #b :m" ??b???%??b,,, #9 :m" ??9???%??9,,, #= :m" ??=???%??=,,, #7 gam" ??7???%??,,,, #> gam" ?8????%?8=,,, #8? gam" ?87???% ?8,,,, #88 gam" ?a????%?a=,,, #8a gam" ?a7???% ?a,,,, #8g gam" ?g????%?g=,,, #8: gam" ?g7???%?g,,,, #8b gam" ?:????%?:=,,, #89 gam" ?:7???% ?:,,,, #8= gam" ?b????%?b=,,, #87 gam" ?b7???% ?b,,,, #8> gam" ?9????%?9=,,, #a? gam" ?97???% ?9,,,, #a8 gam" ?=????%?==,,, #aa gam" ?=7???% ?=,,,, #ag gam" ?7????%?7=,,, #a: gam" ?77???% ?7,,,, #ab gam" ?>????%?>=,,, #a9 gam" ?>7???% ?>,,,, #a= gam" ?#????%?#=,,, #a7 gam" ?#7???%?#,,,, #a> gam" ?;????%?;=,,, #g? gam" ?;7???%?;,,,, #g8 gam" ?!????%?!=,,, #ga gam" ?!7???%?!,,,, #gg gam" ?????%?=,,, #g: gam" ?7???%?,,,, #gb gam" ?-????%?-=,,, #g9 gam" ?-7???%?-,,,, #g= gam" ?,????%?,=,,, #g7 gam" ?,7???%?,,,,,
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 49 preliminary ; '! #g> gam" 8?????%8?=,,, #:? gam" 8?7???% 8?,,,, #:8 gam" 88????%88=,,, #:a gam" 887???% 88,,,, #:g gam" 8a????%8a=,,, #:: gam" 8a7???% 8a,,,, #:b gam" 8g????%8g=,,, #:9 gam" 8g7???%8g,,,, #:= gam" 8:????%8:=,,, #:7 gam" 8:7???% 8:,,,, #:> gam" 8b????%8b=,,, #b? gam" 8b7???% 8b,,,, #b8 gam" 89????%89=,,, #ba gam" 897???% 89,,,, #bg gam" 8=????%8==,,, #b: gam" 8=7???% 8=,,,, #bb gam" 87????%87=,,, #b9 gam" 877???% 87,,,, #b= gam" 8>????%8>=,,, #b7 gam" 8>7???% 8>,,,, #b> gam" 8#????%8#=,,, #9? gam" 8#7???%8#,,,, #98 gam" 8;????%8;=,,, #9a gam" 8;7???%8;,,,, #9g gam" 8!????%8!=,,, #9: gam" 8!7???%8!,,,, #9b gam" 8????%8=,,, #99 gam" 87???%8,,,, #9= gam" 8-????%8-=,,, #97 gam" 8-7???%8-,,,, #9> gam" 8,????%8,=,,, #=? gam" 8,7???%8,,,,, table 12. ws128j sector address table 4
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50 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ; '! #=8 gam" a?????%a?=,,, #=a gam" a?7???% a?,,,, #=g gam" a8????%a8=,,, #=: gam" a87???% a8,,,, #=b gam" aa????%aa=,,, #=9 gam" aa7???% aa,,,, #== gam" ag????%ag=,,, #=7 gam" ag7???%ag,,,, #=> gam" a:????%a:=,,, #7? gam" a:7???% a:,,,, #78 gam" ab????%ab=,,, #7a gam" ab7???% ab,,,, #7g gam" a9????%a9=,,, #7: gam" a97???% a9,,,, #7b gam" a=????%a==,,, #79 gam" a=7???% a=,,,, #7= gam" a7????%a7=,,, #77 gam" a77???% a7,,,, #7> gam" a>????%a>=,,, #>? gam" a>7???% a>,,,, #>8 gam" a#????%a#=,,, #>a gam" a#7???%a#,,,, #>g gam" a;????%a;=,,, #>: gam" a;7???%a;,,,, #>b gam" a!????%a!=,,, #>9 gam" a!7???%a!,,,, #>= gam" a????%a=,,, #>7 gam" a7???%a,,,, #>> gam" a-????%a-=,,, #8?? gam" a-7???%a-,,,, #8?8 gam" a,????%a,=,,, #8?a gam" a,7???%a,,,,, table 12. ws128j sector address table 4
- ) )), k#*

august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 51 preliminary ; '! #8?g gam" g?????%g?=,,, #8?: gam" g?7???%g?,,,, #8?b gam" g8????%g8=,,, #8?9 gam" g87???%g8,,,, #8?= gam" ga????%ga=,,, #8?7 gam" ga7???%ga,,,, #8?> gam" gg????%gg=,,, #88? gam" gg7???%gg,,,, #888 gam" g:????%g:=,,, #88a gam" g:7???%g:,,,, #88g gam" gb????%gb=,,, #88: gam" gb7???%gb,,,, #88b gam" g9????%g9=,,, #889 gam" g97???%g9,,,, #88= gam" g=????%g==,,, #887 gam" g=7???%g=,,,, #88> gam" g7????%g7=,,, #8a? gam" g77???%g7,,,, #8a8 gam" g>????%g>=,,, #8aa gam" g>7???%g>,,,, #8ag gam" g#????%g#=,,, #8a: gam" g#7???%g#,,,, #8ab gam" g;????%g;=,,, #8a9 gam" g;7???%g;,,,, #8a= gam" g!????%g!=,,, #8a7 gam" g!7???%g!,,,, #8a> gam" g????%g=,,, #8g? gam" g7???%g,,,, #8g8 gam" g-????%g-=,,, #8ga gam" g-7???%g-,,,, #8gg gam" g,????%g,=,,, #8g: gam" g,7???%g,,,,, table 12. ws128j sector address table 4
- ) )), k#*

52 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ; '; #8gb gam" :?????%:?=,,, #8g9 gam" :?7???%:?,,,, #8g= gam" :8????%:8=,,, #8g7 gam" :87???%:8,,,, #8g> gam" :a????%:a=,,, #8:? gam" :a7???% :a,,,, #8:8 gam" :g????%:g=,,, #8:a gam" :g7???%:g,,,, #8:g gam" ::????%::=,,, #8:: gam" ::7???% ::,,,, #8:b gam" :b????%:b=,,, #8:9 gam" :b7???% :b,,,, #8:= gam" :9????%:9=,,, #8:7 gam" :97???% :9,,,, #8:> gam" :=????%:==,,, #8b? gam" :=7???% :=,,,, #8b8 gam" :7????%:7=,,, #8ba gam" :77???% :7,,,, #8bg gam" :>????%:>=,,, #8b: gam" :>7???% :>,,,, #8bb gam" :#????%:#=,,, #8b9 gam" :#7???%:#,,,, #8b= gam" :;????%:;=,,, #8b7 gam" :;7???%:;,,,, #8b> gam" :!????%:!=,,, #89? gam" :!7???%:!,,,, #898 gam" :????%:=,,, #89a gam" :7???%:,,,, #89g gam" :-????%:-=,,, #89: gam" :-7???%:-,,,, #89b gam" :,????%:,=,,, #899 gam" :,7???%:,,,,, table 12. ws128j sector address table 4
- ) )), k#*

august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 53 preliminary ; '; #89= gam" b?????%b?=,,, #897 gam" b?7???% b?,,,, #89> gam" b8????%b8=,,, #8=? gam" b87???% b8,,,, #8=8 gam" ba????%ba=,,, #8=a gam" ba7???% ba,,,, #8=g gam" bg????%bg=,,, #8=: gam" bg7???%bg,,,, #8=b gam" b:????%b:=,,, #8=9 gam" b:7???% b:,,,, #8== gam" bb????%bb=,,, #8=7 gam" bb7???% bb,,,, #8=> gam" b9????%b9=,,, #87? gam" b97???% b9,,,, #878 gam" b=????%b==,,, #87a gam" b=7???% b=,,,, #87g gam" b7????%b7=,,, #87: gam" b77???% b7,,,, #87b gam" b>????%b>=,,, #879 gam" b>7???% b>,,,, #87= gam" b#????%b#=,,, #877 gam" b#7???%b#,,,, #87> gam" b;????%b;=,,, #8>? gam" b;7???%b;,,,, #8>8 gam" b!????%b!=,,, #8>a gam" b!7???%b!,,,, #8>g gam" b????%b=,,, #8>: gam" b7???%b,,,, #8>b gam" b-????%b-=,,, #8>9 gam" b-7???%b-,,,, #8>= gam" b,????%b,=,,, #8>7 gam" b,7???%b,,,,, table 12. ws128j sector address table 4
- ) )), k#*

54 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ; '; #8>> gam" 9?????%9?=,,, #a?? gam" 9?7???% 9?,,,, #a?8 gam" 98????%98=,,, #a?a gam" 987???% 98,,,, #a?g gam" 9a????%9a=,,, #a?: gam" 9a7???% 9a,,,, #a?b gam" 9g????%9g=,,, #a?9 gam" 9g7???%9g,,,, #a?= gam" 9:????%9:=,,, #a?7 gam" 9:7???% 9:,,,, #a?> gam" 9b????%9b=,,, #a8? gam" 9b7???% 9b,,,, #a88 gam" 99????%99=,,, #a8a gam" 997???% 99,,,, #a8g gam" 9=????%9==,,, #a8: gam" 9=7???% 9=,,,, #a8b gam" 97????%97=,,, #a89 gam" 977???% 97,,,, #a8= gam" 9>????%9>=,,, #a87 gam" 9>7???% 9>,,,, #a8> gam" 9#????%9#=,,, #aa? gam" 9#7???%9#,,,, #aa8 gam" 9;????%9;=,,, #aaa gam" 9;7???%9;,,,, #aag gam" 9!????%9!=,,, #aa: gam" 9!7???%9!,,,, #aab gam" 9????%9=,,, #aa9 gam" 97???%9,,,, #aa= gam" 9-????%9-=,,, #aa7 gam" 9-7???%9-,,,, #aa> gam" 9,????%9,=,,, #ag? gam" 9,7???%9,,,,, table 12. ws128j sector address table 4
- ) )), k#*

august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 55 preliminary ; '# #ag8 gam" =?????%=?=,,, #aga gam" =?7???%=?,,,, #agg gam" =8????%=8=,,, #ag: gam" =87???%=8,,,, #agb gam" =a????%=a=,,, #ag9 gam" =a7???%=a,,,, #ag= gam" =g????%=g=,,, #ag7 gam" =g7???%=g,,,, #ag> gam" =:????%=:=,,, #a:? gam" =:7???% =:,,,, #a:8 gam" =b????%=b=,,, #a:a gam" =b7???% =b,,,, #a:g gam" =9????%=9=,,, #a:: gam" =97???% =9,,,, #a:b gam" ==????%===,,, #a:9 gam" ==7???% ==,,,, #a:= gam" =7????%=7=,,, #a:7 gam" =77???% =7,,,, #a:> gam" =>????%=>=,,, #ab? gam" =>7???% =>,,,, #ab8 gam" =#????%=#=,,, #aba gam" =#7???%=#,,,, #abg gam" =;????%=;=,,, #ab: gam" =;7???%=;,,,, #abb gam" =!????%=!=,,, #ab9 gam" =!7???%=!,,,, #ab= gam" =????%==,,, #ab7 gam" =7???%=,,,, #ab> gam" =-????%=-=,,, #a9? gam" =-7???%=-,,,, #a98 gam" =,????%=,=,,, #a9a :m" =,7???%=,7,,, #a9g :m" =,>???%=,>,,, #a9: :m" =,#???%=,#,,, #a9b :m" =,;???%=,;,,, #a99 :m" =,!???%=,!,,, #a9= :m" =,???%=,,,, #a97 :m" =,-???%=,-,,, #a9> :m" =,,???%=,,,,, table 12. ws128j sector address table 4
- ) )), k#*

56 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ta b l e 1 3 . ws064j sector address table 4
- ) )), k#*
; ' #? :m" ??????%???,,, #8 :m" ??8???%??8,,, #a :m" ??a???%??a,,, #g :m" ??g???%??g,,, #: :m" ??:???%??:,,, #b :m" ??b???%??b,,, #9 :m" ??9???%??9,,, #= :m" ??=???%??=,,, #7 gam" ??7???% ??,,,, #> gam" ?8????%?8=,,, #8? gam" ?87???% ?8,,,, #88 gam" ?a????%?a=,,, #8a gam" ?a7???% ?a,,,, #8g gam" ?g????%?g=,,, #8: gam" ?g7???%?g,,,, #8b gam" ?:????%?:=,,, #89 gam" ?:7???% ?:,,,, #8= gam" ?b????%?b=,,, #87 gam" ?b7???% ?b,,,, #8> gam" ?9????%?9=,,, #a? gam" ?97???% ?9,,,, #a8 gam" ?=????%?==,,, #aa gam" ?=7???% ?=,,,,
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 57 preliminary ; '! #ag gam" ?7????%?7=,,, #a: gam" ?77???% ?7,,,, #ab gam" ?>????%?>=,,, #a9 gam" ?>7???% ?>,,,, #a= gam" ?#????%?#=,,, #a7 gam" ?#7???%?#,,,, #a> gam" ?;????%?;=,,, #g? gam" ?;7???%?;,,,, #g8 gam" ?!????%?!=,,, #ga gam" ?!7???%?!,,,, #gg gam" ?????%?=,,, #g: gam" ?7???%?,,,, #gb gam" ?-????%?-=,,, #g9 gam" ?-7???%?-,,,, #g= gam" ?,????%?,=,,, #g7 gam" ?,7???%?,,,,, #g> gam" 8?????%8?=,,, #:? gam" 8?7???% 8?,,,, #:8 gam" 88????%88=,,, #:a gam" 887???% 88,,,, #:g gam" 8a????%8a=,,, #:: gam" 8a7???% 8a,,,, #:b gam" 8g????%8g=,,, #:9 gam" 8g7???%8g,,,, ta b l e 1 3 . w s 0 6 4 j s e c t o r a d d r e s s ta b l e 4
- ) )), k#*

58 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ; '! #:= gam" 8:????%8:=,,, #:7 gam" 8:7???% 8:,,,, #:> gam" 8b????%8b=,,, #b? gam" 8b7???% 8b,,,, #b8 gam" 89????%89=,,, #ba gam" 897???% 89,,,, #bg gam" 8=????%8==,,, #b: gam" 8=7???% 8=,,,, #bb gam" 87????%87=,,, #b9 gam" 877???% 87,,,, #b= gam" 8>????%8>=,,, #b7 gam" 8>7???% 8>,,,, #b> gam" 8#????%8#=,,, #9? gam" 8#7???%8#,,,, #98 gam" 8;????%8;=,,, #9a gam" 8;7???%8;,,,, #9g gam" 8!????%8!=,,, #9: gam" 8!7???%8!,,,, #9b gam" 8????%8=,,, #99 gam" 87???%8,,,, #9= gam" 8-????%8-=,,, #97 gam" 8-7???%8-,,,, #9> gam" 8,????%8,=,,, #=? gam" 8,7???%8,,,,, ta b l e 1 3 . w s 0 6 4 j s e c t o r a d d r e s s ta b l e 4
- ) )), k#*

august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 59 preliminary ; '; #=8 gam" a?????%a?=,,, #=a gam" a?7???% a?,,,, #=g gam" a8????%a8=,,, #=: gam" a87???% a8,,,, #=b gam" aa????%aa=,,, #=9 gam" aa7???% aa,,,, #== gam" ag????%ag=,,, #=7 gam" ag7???%ag,,,, #=> gam" a:????%a:=,,, #7? gam" a:7???% a:,,,, #78 gam" ab????%ab=,,, #7a gam" ab7???% ab,,,, #7g gam" a9????%a9=,,, #7: gam" a97???% a9,,,, #7b gam" a=????%a==,,, #79 gam" a=7???% a=,,,, #7= gam" a7????%a7=,,, #77 gam" a77???% a7,,,, #7> gam" a>????%a>=,,, #>? gam" a>7???% a>,,,, #>8 gam" a#????%a#=,,, #>a gam" a#7???%a#,,,, #>g gam" a;????%a;=,,, #>: gam" a;7???%a;,,,, ta b l e 1 3 . w s 0 6 4 j s e c t o r a d d r e s s ta b l e 4
- ) )), k#*

60 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ; '; #>b gam" a!????%a!=,,, #>9 gam" a!7???%a!,,,, #>= gam" a????%a=,,, #>7 gam" a7???%a,,,, #>> gam" a-????%a-=,,, #8?? gam" a-7???%a-,,,, #8?8 gam" a,????%a,=,,, #8?a gam" a,7???%a,,,,, #8?g gam" g?????%g?=,,, #8?: gam" g?7???%g?,,,, #8?b gam" g8????%g8=,,, #8?9 gam" g87???%g8,,,, #8?= gam" ga????%ga=,,, #8?7 gam" ga7???%ga,,,, #8?> gam" gg????%gg=,,, #88? gam" gg7???%gg,,,, #888 gam" g:????%g:=,,, #88a gam" g:7???%g:,,,, #88g gam" gb????%gb=,,, #88: gam" gb7???%gb,,,, #88b gam" g9????%g9=,,, #889 gam" g97???%g9,,,, #88= gam" g=????%g==,,, #887 gam" g=7???%g=,,,, ta b l e 1 3 . w s 0 6 4 j s e c t o r a d d r e s s ta b l e 4
- ) )), k#*

august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 61 preliminary ; '# #88> gam" g7????%g7=,,, #8a? gam" g77???%g7,,,, #8a8 gam" g>????%g>=,,, #8aa gam" g>7???%g>,,,, #8ag gam" g#????%g#=,,, #8a: gam" g#7???%g#,,,, #8ab gam" g;????%g;=,,, #8a9 gam" g;7???%g;,,,, #8a= gam" g!????%g!=,,, #8a7 gam" g!7???%g!,,,, #8a> gam" g????%g=,,, #8g? gam" g7???%g,,,, #8g8 gam" g-????%g-=,,, #8ga gam" g-7???%g-,,,, #8gg gam" g,????%g,=,,, #8g: :m" g,7???%g,7,,, #8gb :m" g,>???%g,>,,, #8g9 :m" g,#???%g,#,,, #8g= :m" g,;???%g,;,,, #8g7 :m" g,!???%g,!,,, #8g> :m" g,???%g,,,, #8:? :m" g,-???%g,-,,, #8:8 :m" g,,???%g,,,,, ta b l e 1 3 . w s 0 6 4 j s e c t o r a d d r e s s ta b l e 4
- ) )), k#*

62 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary command definitions .
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64 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ta b l e 1 4 . programmable wait state settings :;#;
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66 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ta b l e 1 7 . configuration register 0j ; #$
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 67 preliminary autoselect command sequence

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68 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary

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70 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 75 preliminary ' '
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76 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary command definitions ta b l e 1 8 . command definitions
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 77 preliminary
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 79 preliminary write operation status
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 81 preliminary rdy: ready eh

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start no yes yes dq5 = 1? no yes dq6 = toggle? no read byte (dq0-dq7) address = va dq6 = toggle? read byte twice (dq 0-dq7) adrdess = va read byte (dq0-dq7) address = va fail pass <

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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 83 preliminary 3a" "
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 85 preliminary ta b l e 2 0 . write operation status 0n)
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86 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary figure 8. maximum negative overshoot waveform figure 9. maximum positive overshoot waveform operating ranges
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 87 preliminary dc characteristics cmos compatible 6 1
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88 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary test conditions ta b l e 2 1 . test specifications key to switching waveforms / )"." ; 1

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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 89 preliminary switching waveforms ac characteristics v cc power-up / q/ 1& ,,/#/
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90 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary clk characterization figure 13. clk characterization

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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 91 preliminary ac characteristics synchronous/burst read @ v io = 1.8 v ##

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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 93 preliminary ac characteristics 4
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478 figure 17. 8-word linear burst with wrap around da da + 1 da + n oe# data addresses aa avd# rdy clk ce# t cas t aas t avc t avd t aah t oe t racc t oez t cez t iacc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 1234567 t rdys t bacc t acc t cr dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df db 7 cycles for initial access shown. hi-z t racc 1 234567 t rdys t bacc t cr d8 t racc
94 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ac characteristics 4

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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 95 preliminary ac characteristics asynchronous mode read @ v io = 1.8 v

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96 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ac characteristics ###
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0#0 figure 20. asynchronous mode read t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez t aavdh t avdp t aavds avd# ra t cas t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez avd# ra
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 97 preliminary ac characteristics hardware reset (reset#) b,,t
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98 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ac characteristics erase/program operations @ v io = 1.8 v b,,t
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 99 preliminary ac characteristics 224##
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figure 22. asynchronous program operation timings: avd# latched addresses oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph pa t vcs t cs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h 555h pd
100 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ac characteristics 224##
20240 // ###
$# 4

f14
g#f g$

$4 h#3# 4#
@ a
% -. / 1- / 1i ) <

4 4
##$0j ## $ 4 4
figure 23. asynchronous program operation timings: we# latched addresses oe# ce# data addresses avd# we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t acs t cas t ah t csw t avsw
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 101 preliminary ac characteristics 224##
20240 // ###
$# 4

f14
g#f g$

$4 h#3# 4#
@ a
% ##

#$
$
4#4$/0! j#4$-. ) !/0!
@ #4$ ; 4 ;4 4#
@
* <
4 4
##$0j ## $ 4 4
<$ 4 4

## figure 24. synchronous program operation timings: we# latched addresses oe# ce# data addresses avd# we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t acs t cas t ah t avch t csw t avsw
102 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ac characteristics 224##
20240 // ###
$# 4

f14
g#f g$

$4 h#3# 4#
@ a
% ##

#$
$
4#4$/0! j#4$-. ) !/0!
@ #4$ ; 4 ;4 4#
@
* <
4 4
##$0j ## $ 4 4
<$ 4 4

## figure 25. synchronous program operation timings: clk latched addresses oe# ce# data addresses avd# we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t as t cas t ah t avch t csw t avsc
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 103 preliminary ac characteristics figure 26. chip/sector erase command sequence

##
$
##

h#3
# 4 a
#
@ oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph sa t vcs t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h
104 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ac characteristics :

# #
$j 4 figure 27. accelerated unlock bypass programming timing ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id 1 s v il or v ih t vid t vids
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 105 preliminary ac characteristics
#
$ 4
;

// ###
<;#
@ ##

(### 4
#0!2 4; # (

# 0d; ;; #j
###
4 4# figure 28. data# polling timings (during embedded algorithm)
#
$ 4
;

// ###
<;#
@ ##

(### 4
44
;
44 4 (

# 0d; ;; #j
###
4 4# figure 29. toggle bit timings (during embedded algorithm) we# ce# oe# t oe addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data we# ce# oe# t oe addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data
106 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ac characteristics < 4

# 4
// ###
<;#
@ ##

(## # 4
44
;
44 4 0d
j; #7=, $ 4 4
8(= $ 4 4
0d
j a $# figure 30. synchronous data polling timings/toggle bit timings ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc 0n44
;###
;

##
<

&!! 44 0n#0n* figure 31. dq2 vs. dq6 - - - - - -
-
e -
e - .-l 39 3a - ! -

e
- -
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 107 preliminary ac characteristics temporary sector unprotect b,,t
#

)"." b99 ) " ; 0$e 0 $ e , / 4 b?? 022 0 22 e , / 4 ab? e e--l
k 4 : t ee; e--l2eh2 k 4 : t reset# t vidr v id v il or v ih v id v il or v ih ce# we# rdy t vidr t rsp program or erase command sequence t rrb figure 32. temporary sector unprotect timing diagram
108 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ac characteristics sector protect: 150 s sector unprot ect: 1.5 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector protect/unprotect verify v id v ih m
*, ,,
* ,, figure 33. sector/sector block prot ect and unprotect timing diagram
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 109 preliminary ac characteristics 0d j; #7=, $ 4 4
8 0d j a $#7= $ 4 4
8 66 #
a 44
066
k$6 *, 44
0*, 4
;
#j
4a
$$ 4
4 % 1$
4##
#
7
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4 figure 34. latency with boundary crossing clk address (hex) c60 c61 c62 c63 c63 c63 c64 c65 c66 c67 d60 d61 d62 d63 d64 d65 d66 d67 (stays high) avd# rdy data address boundary occurs every 64 words, beginning at address 00003fh: 00007fh, 0000bfh, etc. address 000000h is also a boundary crossing. 3c 3d 3e 3f 3f 3f 40 41 42 43 latency rdy latency t racc (note 1) (note 2) t racc t racc t racc
110 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ac characteristics 0d j; #7=, $ 4 4
8 0d j a $#7= $ 4 4
8 66 #
a 44
066
k$6 *, 44
0*, 4
;
#j
4a
$$ 4
4 figure 35. latency with boundary crossing into program/erase bank clk address (hex) c60 c61 c62 c63 c63 c63 c64 d60 d61 d62 d63 read status (stays high) avd# rdy data oe#, ce# (stays low) address boundary occurs every 64 words, beginning at address 00003fh: 00007fh, 0000bfh, etc. address 000000h is also a boundary crossing. 3c 3d 3e 3f 3f 3f 40 latency rdy latency t racc (note 1) (note 2) t racc t racc t racc invalid
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 111 preliminary ac characteristics
a14, a13, a12 = ?111? ? reserved a14, a13, a12 = ?110? ? reserved a14, a13, a12 = ?101? ? 5 programmed, 7 total a14, a13, a12 = ?100? ? 4 programmed, 6 total a14, a13, a12 = ?011? ? 3 programmed, 5 total a14, a13, a12 = ?010? ? 2 programmed, 4 total a14, a13, a12 = ?001? ? 1 programmed, 3 total a14, a13, a12 = ?000? ? 0 programmed, 2 total 4

##
0,
##
# j a#4

4 #;

f,g figure 36. example of wait states insertion data avd# oe# clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following addresses being latched rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles p ro g rammed 45
112 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ac characteristics 9a
;j$
#

##$f
ag; a 4

$4
f
ga<

##

;
j # $ figure 37. back-to-back read/write cycle timings oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 113 preliminary erase and programming performance < 4#

$ ; 4#
l) =// ,, ,,,
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publication number S71WS-J_04 revision a amendment 2 issue date august 19, 2005 features 3 )

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!! 6 :4%74%ga4 6 74%894%9:4 pin description (32m) cosmoram 32mbit (2m word x 16-bit) 64mbit (4m word x 16-bit) preliminary pin name description # a8 # ? #$
(# a? # ? ga4# a8 # ? 9:4 !-8l !- "# !-a !- 2# .-l .- "# 1-l 1

- "# k;l k;! "# ;l ";! "# ! m ! '$
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 115 preliminary functional description asynchronous operation (page mode)
-/ 1- i/ 1i > / 1- / 1i i 4vi 41# #a
4 # 4r
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/ #i 4v# # 4 j $:9!#-9! 9a 9#e :7 (e @9e .9e :4e ;4e a#26 g 02# g #*2& @/e 2 2 r r r r r r r 2%q 2%q 2%q 1

/8 2 r /g 2 2 r r /b 2%q 2%q 2%q 1

/e r 2 2 2 0 2%q 2%q 2%q ek; r 2 0 2%q 1

0 2%q e "; r 2 0 1

0 2%q 2%q e. r 0 1

0 1

0 2%q e r i2 i2 0 /9 /9 2%q /. r 2 /: 2 2 0 $ $ 2%q .k; r 2 0 $ $
0 2%q . "; r 2 0 $
0 $ 2%q .. r 0 $
0 $
0 2%q "" /a r r r r r r r r 2%q 2%q 2%q
116 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary functional description synchronous operation (burst mode)
-/ 1- i/ 1i > / 1- / 1i // ##4 2-22
j#4$-;2
i 4 vi 41# #a
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1j #i 4v## 4 j $:9!#-9! 1 $(!- 1
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6$

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#$f(1 (1# j i 4 j # 4; 9a 9#e :7 (e @9e .9e :4e ;4e a#26 g 02# g #*2& @/e 2 2 r r r r r r r 2%q 2%q 2%q # /8 0- /g - r /: r /: r /9 r /9 0 /= 2%q /7 2%q /7 2%q /88 # ;
e/+ #/8 0- /g 2 2 r 1

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.
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 117 preliminary state diagrams initial/standby state asynchronous op eration state figure 38. initial standby state diagram figure 39. asynchronous operation state diagram asynchronous operation (page mode) synchronous operation (burst mode) common state cr set power down standby standby power up pause time ce2=h ce2=l power down ce2=h @rp=1 ce2=l @m=0 @m=1 ce2=h @rp=0 (64m only) standby output disable write read ce2=ce1# = h ce1# = h address change or byte control byte control byte control @oe# = l ce1# = h ce1# = h ce1# = l we# = h we# = l oe# = h oe# = l ce1# = l & oe# = l ce1# = l & we# = l
118 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary synchronous operation state

$ # w

w

$ #$w 0
w
w

w
#w < 40 4
w
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j $*% functional description

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cr set sequence !e
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figure 40. synchronous operation diagram cycle # operation address data 8 e g,,,,,4; ee a . g,,,,, e standby write read read suspend write suspend ce2 = ce1# = h ce1# = h ce1# = h we# = h we# = l a dv# low pulse adv# low pulse (@bl = 8 or 16, and after burst operation is completed) ce1# = l adv# low pulse & we# = l ce1# = l adv# low pulse & oe# = l adv# low pulse oe# = l oe# = h ce1# = h ce1# = h
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 119 preliminary 4; "4;$ " % !e " " $ " 'e 4;
"4; v% $ " !e
" " " ' # e 1 !e
!e " !e" !e %

i"

g . g,,,,, e : . g,,,,, r b . g,,,,, r 9 e #m ee cycle # operation address data
120 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary address key '" #*,
fg
1
#
a 1$, 4

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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 121 preliminary power down "" "" !-a!-a " "" "" !-a ' "!-a2
"" "" i" - "

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/ /i#
/ /i# :4 :4 ???????g,,,, 74 74 ?????? ?=,,,, 74 74 ?????? ?=,,,, 894 894 ?????? ?,,,,,
122 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary clk input function ! m
&

n" ! m
%
! m

"

! m

+ "" ! m v

figure 41. burst read operation figure 42. burst write operation a ddress adv# clk dq valid ce1# oe# wait# high-z high-z rl bl q 2 q bl q 1 we# high a ddress adv# clk dq valid ce1# oe# wait# high-z high-z rl-1 bl d 2 d bl d 1 we# high
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 123 preliminary adv# input function #0l

$
"
#0l

!-8lo !-8lo2#0l
# #0l

i" #0lo2 %
1 #0l
2 #0l "

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124 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary latency e e
' "

% $
!e
"%
1 e
!e
"
' % " "
e %8
" + " e !ee o9 9:4 figure 43. read latency diagram address adv# clk valid q1 q2 q3 d1 d2 d3 d4 0 12 345 rl=3 q4 d5 dq [out] dq [in] ce1# oe# or we# wait# wait# 6 q5 d5 q1 q2 d1 d2 d3 rl=4 q3 d4 dq [out] dq [in] wait# wait# q4 d5 q1 d1 d2 rl=5 q2 d3 dq [out] dq [in] wait# wait# q3 d4 high-z high-z high-z high-z high-z high-z d1 rl=6 q1 d2 dq [out] dq [in] wait# wait# q2 d3 high-z high-z
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 125 preliminary address latch by adv# #0l

%

i" #0l" !-8lo

#0lo
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e
0
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#0l !-8l" #

#0lo burst length ;

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!e start address (a6-a0) read address sequence bl = 8 bl = 16 continuous ?? ??%?8%?a%%?9%?= ??%?8%?a%%?-%?, ??%?8%?a%?g%?:% ?8 ?8%?a%?g%%?=%?? ?8%?a%?g%%?,%?? ?8%?a%?g%?:%?b% ?a ?a%?g%%?=%??%?8 ?a%?g%%?,%??%?8 ?a%?g%?:%?b%?9% ?g ?g%%?=%??%?8%?a ?g%%?,%??%?8%?a ?g%?:%?b%?9%?=% =! =!%%=,%=7%%=; =!%%=,%=?%%=; =!%=%=-%=,%7?%78% = =%=-%=,%=7%%=! =%=-%=,%=?%%=! =%=-%=,% @/ %7?%78% =- =-%=,%=7%=>%%= =-%=,%=?%=8%%= =-%=,% @/ % @/ %7?%78% =, =,%=7%=>%=#%%=- =,%=?%=8%=a%%=- =,% @/ % @/ % @/ %7?%78
126 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary write control ".-l ).-l ! * ).-l ! '
! *
" $ %

!e
burst read suspend ;

1-l2

% 1-l
2

1 1-l
2"
'"

%
$

1-l
"

1 1-l
"

1-lo2

1-lo $

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figure 44. write controls address adv# clk valid 0 12 345 ce1# we# 6 d1 d2 rl=5 d3 dq [in] wait# d4 we# d1 d2 d3 dq [in] wait# d4 high-z t wld high-z t wsck t ckwh t wlth t clth we# level control we# single clock pulse control t wlth
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 127 preliminary burst write suspend ;
"
.-l2

" .-l
2

" 1 .-l
2"
'"

$ %

" .-l
"

" 1 .-l
"

" "
% "
.-lo $

.-lo
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;
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" burst read termination ;
!-8l
2$; !

figure 45. burst read suspend diagram figure 46. burst write suspend diagram q 2 dq oe# clk q 1 t ac t ckqx t olz t ac q 2 t ckqx t ac q 3 t ckqx t ac t ckoh t osck t ckoh t osck t ohz wait# t cktv q 4 dq we# d 1 t dhck t dsck t dsck d 2 t dhck t dsck t dsck d 3 t dhck t dsck t dsck t ckwh t wsck t ckwh t wsck d 2 d 4 wait# high clk
128 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary !-8lo2$

$

!-8lo '
# %

" burst write termination ;
" !-8l
2$; !

"

!-8lo2$
" $
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!-8lo '
#

" figure 47. burst read termination diagram figure 48. burst write termination diagram a ddress adv# dq oe# clk valid ce1# wait# q 1 q 2 t ac t ckqx t ckclh t trb t ckoh t chz high-z t chtz t ohz a ddress adv# dq we# clk valid ce1# wait# t ckclh t trb t ckwh t chtz high-z d 2 d 1 t dhck t dhck t dsck t dsck t chck
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 129 preliminary absolute maximum ratings ( b 1b e l # # j
# 4 # $

7j 4 8 6
$
6 4
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4
recommended operating conditi ons (see warning below) 6 0j 4 #1?&
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package pin capacitance ( # oabc!o8?42& item symbol value unit 00
e0 0 %?bdg9 0 0# e0 0 $/ 0 1k %?bdg9 0 !
1

!
$ 1k wb? #
< %bbd8ab c! parameter symbol 32m 64m unit min max min max
0 0 89b 8>b 8= 8>b 0 0 ? ? ? ? 0 2 $
0/8 0 $2 0 +?7 0 d?a 0 +?7 0 d?a 0 2 $
0/a 0 $ %?g 0 +?a %?g 0 +?a 0 #
# %g? 7b %g? 7b c! symbol description te s t s e t u p ty p max unit ! $/8 #$
! 0 $/ o?0 6 b , ! $/a ! $
! 0 $/ o?0 6 b , ! $1 $
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130 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary dc characteristics (under recommended conditions unless otherwise noted) j 4
$#/ 0

#$$ ; 42&(:2 4 1 &:< ##
##

) / da *1 ; $
k$ $
k$ $
' !
$ $ 0 $/ o0 0 %8? d8? %8? d8? # 1

' !
$ 1 0 1k o0 0 1

%8? d8? %8? d8? # 1

20 0 12 0 o0 $ 12 o@?b# a: 6 a: 6 0 1

"0 0 1 $ 1 o8# 6 ?: 6 ?: 0 0 "" !
$ 0 o0 + 0 $/ o0 $2 0 $ !-a ?a0 -- 6 8? 6 ; # $ : :4 6 :? /i# # $ 7 74 6 b? 6 ; # $ 89 894 /i# 6 ; 0 !
$ 0 o0 + 0 $/
! mo0 $2 0 $ !-8lo!-ao0 $2 68b6;# $ 8 0 o0 + 0 $/
! m ?a0 0 $/
! m 0 @?a0 !-8lo!-a 0 @?a0 # d7bc! 6 7? 6 ; t# # d:?c! 6 7? 6 ; t# 0 o0 + !m o 0 $/ ?a00 $/ 0 @?a0 !-8lo!-a 0 @?a0 6a??6; # 0 # !
$ #8 0 o0 + 0 $/ o0 $2 0 $ !-8lo0 $ !-ao0 $2 $ 1k o?# e! i .! o
6g?6gb# $ #a e! i .! o 8 6g6b# 0 e !
$ #g 0 o0 +0 $/ o0 $2 0 $ !-8lo0 $ !-ao0 $2 $ 1k o?# e! o 68?6;# 0 ;
# !
$ #: 0 o0 +0 $/ o0 $2 0 $ !-8lo0 $ !-ao0 $2 !m o !m ; o!

$ 1k o?# 68b6;#
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 131 preliminary ac characteristics (under recommended operating condit ions unless otherwise noted) read operation 6 j
$!
a -;; 4$##
$ ##

# 4#; < #),; ), / 00 m,)/ parameter symbol 32m 64m unit notes min. max. min. max. e! e! =? 8??? =? 8??? 8a !-8l# !- 6 =? 6 =? g 1-l# 1- 6 :? 6 :? g ## ## 6 =? 6 =? gb #0l# #0 =? =? g ;lik;l# ;# 6 g? 6 g? g ## ## 6 a? 6 a? g9 e! e! a? 8??? a? 8??? 89= 1

2 12 b 6 b 6 g !-8l "1

"%q ! q b 6 b 6 : 1-l "1

"%q 1 q 8? 6 ? 6 : ;lik;l "1

"%q ; q ? 6 ? 6 : !-8l21

2%q !2q 6 a? 6 a? g 1-l21

2%q 12q 6 a? 6 a? g ;lik;l21

2%q ;2q 6 a? 6 a? g #
!-8l " #! @b 6 @b 6 #
1-l " #1 8? 6 8? 6 #0l "
. 0 8? 6 8? 6 7 #0l2
. 02 8b 6 8b 6 7 #
#02 #0 b 6 b 6 #2#0l2 #20 8? 6 b 6 #$ #r 6 8? 6 8? b> #2!-8l2 !2#2 @b 6 @b 6 8? #21-l2 12#2 @b 6 @b 6 8? .-l21-l "e .21 8b 8??? ab 8??? 88 !-8l2
. ! 8b 6 8b 6
132 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary % < #); # ) ;!
a-; * , #;!
a-;$4##

' 1
24#
#; a 4!

-; !
4i 4; %r
1 ;#
24#

#; %r
= /2-

$ #$4 j#4$ !0/!; j
<
$ /2- # /2i
@ 4$
5 ##

;
; $##

; #$j

, 7 8# 2 7 8

$ # 1$ j $ (i&-

$ # j
$$ ; 4# 4 $
4 j $
$ # j
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 133 preliminary write operation 6 j
$!
a-;; ##
4 j
@ 4
$;
7 ( (2 9( 8#; j 7 ( 8 (

#$ #$i 4-;
$! (! -9!?:9! ; j

% /2-

$ #$4 j#4$ !0/!; j
<
$ /2- # /2i
@ 4 ( $
) $
a 9
a

#$ #i 4-;
$!(!; j

* $
a 9
a #
#$ #$-; i 4
$!(!; j
$
' ( j
#$ #$-;i 4
$! (! -9!?:9! ; j
$
= 1$&!
-;$ &i- #
#1;#
& !
4i 4; )
$ !
4-;&#
# ;;

# $
5 1$&!
-;$;##
#
#1;# &!
4i 4
$;##
j #&#
# ;;

# $
##

i 4v parameter symbol 32m 64m unit notes min. max. min. max. .! .! =? 8??? =? 8??? 8a #
# ? 6 ? 6 g #0l "
. 0 8? 6 8? 6 : #0l2
. 02 8b 6 8b 6 #
#0l2 #0 b 6 b 6 #2#0l2 #20 8? 6 b 6 !-8l.
. !. :b 6 :b 6 g .-l.
. . :b 6 :b 6 g ;lik;l.
. ;. :b 6 :b 6 g ;lik;l;4'
; %b 6 %b 6 b ;lik;l;4'2 ;2 %b 6 %b 6 9 !-8l.e .e! 8b 6 8b 6 = .e .e 8b 8??? 8b 8??? = !-8l2
. ! 8b 6 8b 6 .-l2
. .2 8b 8??? 8b 8??? ;lik;l2
. ;2 8b 8??? 8b 8???
8b 6 8b 6 2 2 ? 6 ? 6 1-l2!-8l "
. 12! %b 6 %b 6 7 1-l2#
. 1- ? 6 ? 6 > ;lik;l.
1 ;.1 g? 6 g? 6
134 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary synchronous operation - clo ck input (burst mode) a #
#$ #;j # a#4
a
?$
#$ #;/ 1i #/ 1- 6 synchronous operation - address latch (burst mode) -
$!
4 -;$0/!
4-; /-
$0/!
4 -;$!
4-; /2-

$ #$4 j#4$ !0/!; j
%
j # a#4 parameter symbol 32m 64m unit notes min. max. min. max. ! ' e o9 !m /i# 8g 6 8 e ob 8b 6 8b 6 e o: a? 6 87 6 e og g? 6 g? ! '2 !m2 b 6 : 6 ! ' " !m b 6 : 6 ! 'ei, !m 6 g 6 g a parameter symbol 32m 64m unit notes min. max. min. max. #
#0l " #0 %b 6 %b 6 8 #
!-8l " #! %b 6 %b 6 a #2#0l2 #20 8? 6 b 6 #0l "
. 0 8? 6 8? 6 g #0l "
! m e o9b 0!m = 6 b 6 : e o:g 6 = 6 : !-8 "
! m e o9b ! !m = 6 b 6 : e o:g 6 = 6 : #0l "2! m !m02 8 6 8 6 : ;
- #0l22! m 020 8b 6 8g 6
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 135 preliminary synchronous read operation (burst mode) < #),; ), / 00 m,)/ (1i 4 4 4# # 4&!$ 4#4 4 .4#$ &-<- 768$&!$ 4#4# &.

$ # % < #
); # ) &# #
4# #$
* 0$ #$-;i 4
$!i 4 -;
$ 0/!!; j
parameter symbol 32m 64m unit notes min. max. min. max. ;
e! e!; 6 7??? 6 :??? ! m# e o9b #! 6 8a 6 8? 8 e o:g 6 8a 8 1

2! m !m3r g 6 g 6 8 !-8l ".#$l " ! b a? b a? 8 1-l ".#$l " 1 ? a? ? a? 8a #0l ".#$l " 0 /i# ? a? 8 ! m.#$l0 !m0 6 8a 6 8? 8g .#$l02! m !mr g 6 g 6 8 !-8l "1

"%q ! q b 6 b 6 : 1-l "1

"%q 1 q 8? 6 8? 6 : ;lk;l "1

"%q ; q ? 6 ? 6 : !-8l21

2%q !2q 6 8: 6 a? 8 1-l21

2%q 12q 6 8: 6 a? 8 ;lk;l21

2%q ;2q 6 8: 6 a? 8 !-8l2.#$2%q !2q 6 a? 6 a? 8 1-l2.#$2%q 12q 6 a? 6 a? 8 1-l "
8%
1 3 g? 6 g? 6 k;l ;l
8%
; 3 g? 6 a9 6 b 1-l
! m 1!m b 6 b 6 1-l2! m !m12 b 6 b 6 ;
- !-8l "2! m !m! 2 b 6 b 6 ;
- k;l ;l2! m !m;2 b 6 b 6 ;
e ; o789 e; g? 6 a9 6 9 ; o!

=? 6 =? 6 9
136 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary synchronous write operation (burst mode) 0$ #$j # #4 i 4-;
$ 0/! ! (! ; j

# # #
4# #$
< #),; ), / 00 m,)/ 0$ #$j # a#4;
# 4 ##$
; i 4 -;
$ 0/!!; j
$6
% 0$ #$-;i 4
$!i 4 -;
$ 0/!!; j
$6
parameter symbol 32m 64m unit notes min. max. min. max. ;
.! .!; 6 7??? 6 :???
! ' !m = 6 b 6 2! m 2!m g 6 g 6 .-l "
8$ . g? 6 g? 6 k;l ;l
. ; %b 6 %b 6 8 .-l
! m .!m b 6 b 6 .-l2! m !m.2 b 6 b 6 !-8l ".#$l2 ! 2 b a? b a? a .-l ".#$l2 . 2 ? a? ? a? a !-8l2.#$l2%q !2q 6 a? 6 a? a .-l2.#$l2%q .2q 6 a? 6 a? a ;
- !-8l "2! m !m! 2 b 6 b 6 ;
- !-8l2
+! m !2!m b 6 b 6 ;
- k;l ;l2! m !m;2 b 6 b 6 ;
.e .e; g? a9 ;
e ; o789 e; g? 6 a9 6 g ; o!

e; =? 6 =? 6 :
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 137 preliminary power down parameters ;2,7
24#82 7
248#
j $*%
; ;2 #

other timing parameters # 4; ##
$ i(> 7 8

$ # 6$ a
<1<
< 7 < 8
4
)
$

#
$

j 1$ <
4)

$ #

# j
$ $
4
w <
#
w
ac test conditions parameter symbol 32m 64m unit notes min. max. min. max. !-a "
"" - ! a? 6 8? 6 !-a "2"" - !a =? 6 =? 6 !-a "2e#
4 !a e /i# b? 6 t 8 !-8l22" !-a2" " -+[ -- \ !22 g?? 6 g?? 6 t a !-8l22" !-a2" " -+[ --\ !22 =? 6 =? 6 t g !-8l2
" !-a2" " -+ !2 ? 6 ? 6 a parameter symbol 32m 64m unit notes min. max. min. max. !-821-$ - !21r 8? 6 8? 6 !-82.-$ - !2.r 8? 6 8? 6 8 !-a "2"%
!a 2 b? 6 b? 6 t !-822" !-a2"%
!22 g?? 6 g?? 6 t $
8 ab 8 ab a symbol description te s t s e t u p value unit note 0 $2 $
2 0 ^?7 0 0 $ $
" 0 ^?a 0 0 e-, $
4
0 ^?b 0 $
# ;" 0 $ 0 $2 b g
138 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary ac measurement output load circuit figure 49. output load circuit device under test v dd v dd *0.5v v ss out 0.1 f 50pf 50ohm
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 139 preliminary timing diagrams <
4# 4

i#(!i <
4# 4

i#(!i figure 50. asynchronous read timing #1-1 (basic timing) figure 51. asynchronous read timing #1-2 (basic timing) t ce valid data output address ce1# dq (output) oe# t chz t rc t olz t chah t cp address valid t asc t asc t ohz t oh t bhz t oe t ba t blz adv# low lb# / ub# t ce valid data output address ce1# dq (output) oe# t chz t rc t olz t cp t asc t asc t ohz t oh t bhz t oe t ba t blz adv# address valid t ahv t vpl t av lb# / ub#
140 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i 0/!-#(!i <
4# 4

i 0/!-#(!i figure 52. asynchronous read timing #2 (oe# & address access) figure 53. asynchronous read timing #3 (lb# / ub# byte access) t aa valid data output address ce1# dq (output) t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe# t ax low t aa t ohah t aso lb# / ub# t aa valid data output address dq1-8 (output) ub# t bhz t ba t rc t blz address valid valid data output t bhz t oh lb# t ax low t ba t ax dq9-16 (output) t blz t ba t blz t oh t bhz t oh valid data output ce1#, oe#
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 141 preliminary <
4# 4

i#(!i <
4# 4

i 0/!-#(!i -9!#:9!
-;;!#&!-; figure 54. asynchronous read timing #4 (page addr ess access after ce1# control access) figure 55. asynchronous read timing #5 (random and page address access) valid data output (normal access) address (a2-a0) ce1# dq (output) oe# t chz t ce t rc t clz address valid valid data output (page access) address valid t prc t oh t oh t chah t paa address (a21-a3) address valid t paa t oh t prc t paa t prc t oh address valid address valid t rc adv# t asc lb# / ub# valid data output (normal access) address (a2-a0) ce1# dq (output) oe# t oe t rc t olz t blz t aa valid data output (page access) address valid t prc t oh t oh t rc t paa address (a21-a3) address valid t aa t oh address valid t rc t paa t prc t oh address valid address valid t rc t ax t ax t ba address valid low t aso lb# / ub#
142 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i#0/!- <
4# 4

i figure 56. asynchronous write timing #1-1 (basic timing) figure 57. asynchronous write timing #1-2 (basic timing) t as valid data input address ce1# dq (input) we# t dh t ds t wc t wrc t wp t cw t as t bw address valid t as t as t br oe# t ohcl t as t as t wr adv# low lb#, ub# t as valid data input a ddress ce1# dq (input) we# t dh t ds t wc t wrc t wp t cw t as t bw address valid t as t as t br oe# t ohcl t as t as t wr adv# t vpl t ahv lb#, ub#
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 143 preliminary <
4# 4

i#0/!- <
4# 4

i 0/!-#&!i figure 58. asynchronous write timing #2 (we# control) figure 59. asynchronous write timing #3-1 (we# / lb# / ub# byte write control) t as address we# ce1# t wc t wr t wp address valid t as t wr t wp valid data input dq (input) t dh t ds oe# t oes t ohz t wc valid data input t dh t ds low address valid t ohah ub#, lb# t as a ddress we# ce1# t wc t br t wp lb# address valid t as t br t wp valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh
144 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i 0/!-#&!i <
4# 4

i 0/!-#&!i figure 60. asynchronous write timing #3-2 (we# / lb# / ub# byte write control) figure 61. asynchronous write timing #3-3 (we# / lb# / ub# byte write control) t as a ddress we# ce1# t wc t wr t bw lb# address valid t as t wr t bw valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t as a ddress we# ce1# t wc t br t bw lb# address valid t as t br t bw valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 145 preliminary <
4# 4

i 0/!-#&!i <
4# 4

i#0/!- ( ##

j #$ !(!$
$ 4#4 figure 62. asynchronous write timing #3-4 (we# / lb# / ub# byte write control) figure 63. asynchronous read / write timing #1-1 (ce1# control) t as a ddress we# ce1# t wc t br t bw lb# address valid t as t br t bw dq1-8 (input) t dh t ds ub# t wc t dh t ds low address valid dq9-16 (input) t dh t ds t as t br t bw t as t br t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo read data output address ce1# dq we# t wc t cw oe# t ohcl t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wrc t chah t dh t clz t oh ub#, lb#
146 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i#0/!- &!$ 6#-;# 4; $
! #; #( #@ <
4# 4

i#0/!- ! #-;$( !#&! # figure 64. asynchronous read / write timing #1-2 (ce1# / we# / oe# control) figure 65. asynchronous read / write timing #2 (oe#, we# control) read data output address ce1# dq we# t wc t wp oe t ohcl t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output ub#, lb# read data output address ce1# dq we# t wc t wp oe# t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah ub#, lb#
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 147 preliminary <
4# 4

i#0/!- ! #-;$( !#&! # a
@ ## 4!- .
#$ #;j # a#4
.<
#$ #;/ 1i #/ 1- 6 figure 66. asynchronous read / write timing #3 (oe,# we#, lb#, ub# control) figure 67. clock input timing read data output a ddress ce1# dq we# t wc t bw oe# t ba write address t as t rc write data input t ds t bhz t oh t aa read address t br t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oes ub#, lb# clk t ck t ckh t ckl t ckt t ckt t ck
148 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary
!
4;!
4-;$0/!
4-;
!
4;0/!
4-;$!
4-; /2-

$ #$4 j#4$ !0/!; j

j # a#4
# 40/!- /. # -. #
j # a#4# 40/!- figure 68. address latch timing (synchronous mode) clk adv# a ddress ce 1# t ahv t vpl t asvl valid case #1 case #2 t vsck t ahv t vpl t vlcl valid t vsck t clck t ascl low t ckvh t ckvh
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 149 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 69. 32m synchronous read timing #1 (oe# control) adv# dq we# oe# valid t asvl t ahv t vpl t clck t ascl wait# q 1 t olq t ac t ckqx t oltl t ac t cktv high q bl high-z rl=5 t vsck t ohtz t olz t ac t ckqx t ohz t rcb t ckoh t cktv valid t vsck t clck t cp t vpl t vhvl high-z t blq t ckbh t ascl t asvl t cktx t cktx t ckvh t ckvh ce1# lb#, ub# address clk
150 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 70. 32m synchronous read timing #2 (ce1# control) addr e ss adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl t clck t ascl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t vsck t clck t cp t vpl t vhvl t cltl high t clz t ckclh t ascl t ahv q bl t chtz t clz t ckqx t chz t cktv t cltl t ckbh t asvl t cktx t cktx t ckvh t ckvh
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 151 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 71. 32m synchronous read timing #3 (adv# control) address adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t asvl t vsck t vpl t vhvl high t ahv q bl t ckqx t cktv low low t cktx t cktx t ckvh t ckvh
152 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 72. synchronous read - wait# output timing (continuous read) xxx7fh t asvl t ahv t vpl t clck t ascl q 1 t olq t ac t ckqx t oltl t ac t cktv high high-z rl=5 t vsck t olz t cktv high-z q 2 t ckqx q 3 t ckqx t ac t ac t cktv t ac t blq t cktx t cktx t cktx t ckvh clk address adv# ce1# oe# we# lb#, ub# wait# dq
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 153 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 73. 64m synchronous read timing #1 (oe# control) t ahv address adv# dq we# oe# clk valid ce1# t asvl t vpl t clck t ascl wait# q 1 t olq t ac t ckqx t oltl t ac t cktv high q bl high-z rl=5 t vsck t ohtz t olz t ac t ckqx t ohz t rcb t ckoh valid t vsck t clck t cp t vpl t vhvl high-z t blq t ckbh t ascl t asvl t cktx t ckvh t ckvh lb#, ub#
154 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 74. 64m synchronous read timing #2 (ce1# control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t vsck t clck t cp t vpl t vhvl t cltl high t clz t ckclh t ascl t ahv q bl t chtz t clz t ckqx t chz t cltl t ckbh t asvl t cktx t ckvh t ckvh lb#, ub#
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 155 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 75. 64m synchronous read timing #3 (adv# control) addr es s adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t asvl t vsck t vpl t vhvl high t ahv q bl t ckqx low low t cktx t vltl t vltl t ckvh t ckvh
156 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 76. synchronous write timing #1 (we# level control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# high high-z rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb t ckwh t wld valid t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t whtz t ckvh t ckvh t asvl lb#, ub#
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 157 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 77. synchronous write timing #2 (we# single clock pulse control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# high high-z rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb t ckclh valid t asvl t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t chtz t wlth t wsck t ckwh t ckwh t wsck t ckvh t ckvh lb#, ub#
158 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 78. synchronous write timing #3 (adv# control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl wait# high rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb valid t asvl t ahv t vpl t vsck t bs t wrb t vsck t vhvl t ckbh high t ckvh t ckvh lb#, ub#
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 159 preliminary <
4# 4

i j # a#4
4 #4#
4 ; ( #
#j # a#4 figure 79. synchronous write timing #4 (we# level control, single write) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# high high-z rl=5 t bs d 1 t dhck t dsck t wcb t ckwh t wld valid t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t whtz t wlth t ckvh t ckvh t asvl lb#, ub#
160 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 80. 32m synchronous read to write timing #1(ce1# control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# t vsck t bs t cp rl=5 d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t chtz t ac t ckqx t chz t ckqx t ckclh t ckclh t cktv t vhvl t ckbh t ckbh t cktx t wcb t ckvh t clth lb#, ub#
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 161 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 81. 32m synchronous read to write timing #2(adv# control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl wait# t vsck t bs rl=5 t ckwh d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t ohtz t ac t ckqx t ohz t ckqx t wld t ckoh t cktv t vhvl t ckbh t ckbh t cktx t ckvh t wlth lb#, ub#
162 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 82. 64m synchronous read to write timing #1(ce1# control) addr ess adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl t clck t ascl wait# t vsck t bs t cp rl=5 d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t chtz t ac t ckqx t chz t ckqx t ckclh t ckclh t vhvl t ckbh t ckbh t wcb t clth t ckvh
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 163 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 83. 64m synchronous read to write timing #2(adv# control) addr es s adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl wait# t bs rl=5 t ckwh d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t ohtz t ac t ckqx t ohz t ckqx t wld t ckoh t vhvl t ckbh t ckbh t wlth t ckvh t vsck
164 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 84. synchronous write to read timing #1 (ce1# control) d bl address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t ckt t clck t ascl wait# t vsck t cp rl=5 t ckclh d bl-1 t dhck t dhck t dsck t dsck q 1 q 2 t ac t ckqx t ac t ckqx t cktv t cltl t clz t wrb t ckbh t cktx t ckvh t chtz high-z lb#, ub#
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 165 preliminary <
4# 4

i j # a#4
4#4#9-=* figure 85. synchronous write to read timing #2 (adv# control) d bl address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t ckt wait# low t vsck rl=5 t ckwh d bl-1 t dhck t dhck t dsck t dsck q 1 q 2 t ac t ckqx t ac t ckqx t cktv t oltl t olz t olq t wrb t blq t ckbh t cktx t ckvh t whtz high-z lb#, ub#
166 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary < -i
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figure 86. power-up timing #1 figure 87. power-up timing #2 figure 88. power down entry and exit timing t c2lh ce1# v dd v dd min 0v ce2 t chh t chs ce1# v dd v dd min 0v ce2 t chh t csp ce1# power down entry ce2 t c2lp t chh (t chhp ) power down mode power down exit t chs dq high-z
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 167 preliminary 9 i&> # i(> #$
4$##1$ $ 4

$ # a
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< ##

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##

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4 7-9!:9!8# -; figure 89. standby entry timing after read or write figure 90. configuration register set timing #1 (asynchronous operation) t chox ce1# oe# we# active (read) standby active (write) standby t chwx address ce1# dq* 3 we# t rc oe# rda msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 t wc t wc t wc t wc t rc t cp t cp t cp t cp t cp cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 rda rda x x rdb t cp * 3 (t rc ) lb#, ub#
168 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary < ##

i 4$ !!) <##
a
$ $
$ # w 0
w
1$ ## 4# $ <9 $ ; 4 !* $ 4 4

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4 7-9!:9!8# -; figure 91. configuration register set timing #2 (synchronous operation) address adv# dq we# oe# clk ce1# wait# rda msb rda msb rda msb x msb x msb rdb key t rcb t wcb t wcb t wcb t wcb t rcb t trb t trb t trb t trb t trb cycle#1 cycle#2 cycle#3 cycle#4 cycle#5 cycle#6 t trb rl rl-1 rl-1 rl-1 rl-1 rl lb#, ub#
publication number S71WS-J_04 revision a amendment 2 issue date august 19, 2005 features 3 )

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e # 4 e#4 89===a89 89%!141e#4 8

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2 # cosmoram type 1 C 1.8 v, 16 mb cmos 1,048,576-word x 16 bit psram preliminary
170 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary pin description block diagram
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 171 preliminary function truth table
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 173 preliminary 6 j
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174 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary power down parameters
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 175 preliminary timing diagrams <
4# 4

i#(!i figure 92. read timing #1 (basic timing) <
4# 4

i#(!i figure 93. read timing #2 (oe# and address access) !- 01

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176 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i#(!i figure 94. read timing #3 (lb# / ub# byte access) <
4# 4

i figure 95. write timing #1 (basic timing) ## 0 1

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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 177 preliminary <
4# 4

i figure 96. write timing #2 (we# control) <
4# 4

i#&!i figure 97. write timing #3 C 1 (we# / lb# / ub# byte write control) # # .-l !-l8 .! .e . ;l k;l # 0 # .e . 0$
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178 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

i#&!i figure 98. write timing #3 C 2 (we# / lb# / ub# byte write control) <
4# 4

i#&!i figure 99. write timing #3 C 3 (we# / lb# / ub# byte write control) # # .-l !-l8 .! .e ;. ;l #0 # .e ;. 0$
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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 179 preliminary <
4# 4

i#&!i figure 100. write timing #3 C 4 (we# / lb# / ub# byte write control) <
4# 4

i ( ##

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180 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary <
4# 4

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@ figure 102. read / write timing #1 C 2 (ce#1 / we# / oe# control) <
4# 4

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august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 181 preliminary <
4# 4

i ! #-;$(!#&! # figure 104. read / write timing #3 ( oe , we , lb , ub control < ii
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figure 106. power-down entry and exit timing # !-l8 3 .-l .! ;. 1- k;l ;l ;# .# # e! .$
;2q 12 ## e# 2 ; q 12 e 1

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!-l8 0 0 ?0 !-a !22 ! !-l8 "" - !a !22 "" 4 "" -+ !2 3 2%q !-a
182 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary 9 i&> # i(> #$
4$## 1$ $ 4

$ # a
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figure 107. standby entry timing after read or write !21r !-l8 1-l .-l # e # . !2.r
august 19, 2005 S71WS-J_04_a2 S71WS-J based mcps 183 preliminary cosmoram type 1 revision summary revision a0 (august 2, 2005) $
184 S71WS-J based mcps S71WS-J_04_a2 august 19, 2005 preliminary revision summary revision a0 (october 27, 2004) $ revision a1 (july 5, 2005) #!?7? '" 4 $ revision a2 (august 19, 2005) #89 4!141e#48

the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon sy stem), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages ari sing in connection with above- mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design me asures into your facility and equipment such as redundancy, fire protection, and prev ention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on ex- port under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government en tity will be required for export of those products.
the contents of this document are subject to change without noti ce. this document may contain information on a spansion llc pro duct under development by spansion llc . spansion llc reserves the right to change or discontinue work on any product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damages of any kind arising out of the use of the informatio n in this document. copyright ?2004-2005 spansion llc. all rights reserved. spansion, the spansion logo, and mirrorbit are trademarks of spansion l lc. other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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